## Abstract Hierarchical redundancy using defectโtolerant replacement circuits is proposed as a means to increase the yield of largeโarea LSIs (WSIs) with meshโconnected array structures. The defectโtolerant replacement circuits can be constructed by using directโconnection paths and distributed sw
Test quality of hierarchical defect-tolerant integrated circuits
โ Scribed by Claude Thibeault; Yvon Savaria; Jean -Louis Houle
- Book ID
- 104648831
- Publisher
- Springer US
- Year
- 1992
- Tongue
- English
- Weight
- 783 KB
- Volume
- 3
- Category
- Article
- ISSN
- 0923-8174
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โฆ Synopsis
This paper presents a theoretical expression to evaluate the test quality of hierarchical defect-tolerant integrated circuits. This expression, which is developed for circuits with two levels of hierarchy, is based on a defect model with which one can take into account the relative importance (probability of occurrence) of each defect and consequently of each fault. Results obtained from this expression show that, for a given test coverage, the addition of defect-tolerance mechanisms decreases the test quality of integrated circuits. These results are important because they indicate that fault coverage can be a misleading measure of the test quality of defect-tolerant integrated circuits.
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