Hierarchical redundancy for two-dimensional orthogonal arrays using defect-tolerant replacement circuits
✍ Scribed by Nobuo Tsuda
- Book ID
- 104591557
- Publisher
- John Wiley and Sons
- Year
- 1993
- Tongue
- English
- Weight
- 847 KB
- Volume
- 24
- Category
- Article
- ISSN
- 0882-1666
No coin nor oath required. For personal study only.
✦ Synopsis
Abstract
Hierarchical redundancy using defect‐tolerant replacement circuits is proposed as a means to increase the yield of large‐area LSIs (WSIs) with mesh‐connected array structures. The defect‐tolerant replacement circuits can be constructed by using direct‐connection paths and distributed switches in basic k‐out‐of‐n redundancy schemes.
When the proposed redundancy configurations are applied to two‐dimensional orthogonal‐array WSIs, they reduce the number of switches not covered by any spare replacements.
An estimate of defect tolerance indicates that the proposed redundancy configurations can increase the integration scale of under 1‐μm CMOS design circuits to about 400 times that of general nonredundant LSIs.