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Test generation at the algorithm-level for gate-level fault coverage

✍ Scribed by Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas

Book ID
108210758
Publisher
Elsevier Science
Year
2008
Tongue
English
Weight
226 KB
Volume
48
Category
Article
ISSN
0026-2714

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An algorithm to generate complete test s
An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits
✍ Leonard J. Tung; David V. Kerns πŸ“‚ Article πŸ“… 1988 πŸ› Elsevier Science 🌐 English βš– 581 KB

A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component