✦ LIBER ✦

Temperature scaling of CMOS circuit power consumption

✍ Scribed by Victor Sverdlov; Yehuda Naveh; Konstantin Likharev

Book ID: 104428636
Publisher: Elsevier Science
Year: 2003
Tongue: English
Weight: 85 KB
Volume: 18
Category: Article
ISSN: 1386-9477
DOI: 10.1016/s1386-9477(02)01056-1

No coin nor oath required. For personal study only.

✦ Synopsis

We have analyzed fundamental physical limitations on power consumption of prospective semiconductor digital integrated circuits based on nanoscale silicon MOSFETs, using simple models of these devices and power dissipation. Results show that the temperature dependence of the power is determined by circuit speed requirements. For high-speed operation, both power P and power supply voltage VDD saturate when T is reduced below approximately 100 K. In the low-speed limit, P scales as T 2 , while VDD drops linearly with T . However, thermal uctuations may alter this scaling, leading to P ˙T and VDD ˙T 1=2 , at low temperatures and/or large circuit densities. We compare this scaling with that of superconductor RSFQ logic.

📜 SIMILAR VOLUMES

Multi-Voltage CMOS Circuit Design (Kursu

Multi-Voltage CMOS Circuit Design (Kursun/Multi-Voltage CMOS Circuit Design) || Sources of Power Consumption in CMOS ICs

✍ Kursun, Volkan; Friedman, Eby G. 📂 Article 📅 2006 🏛 John Wiley & Sons, Ltd 🌐 English ⚖ 662 KB

This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by

Estimating power consumption of CMOS cir

Estimating power consumption of CMOS circuits modelled as symbolic neural networks

✍ Macii, E.; Poncino, M. 📂 Article 📅 1996 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 737 KB

Current Consumption and Power Integrity

Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout

✍ J. M. Ruiz, R. Fernández-Garcia, I. Gil, M. Morata 📂 Article 📅 2012 🏛 Springer US 🌐 English ⚖ 419 KB

A simple voltage scaling formula for low

A simple voltage scaling formula for low-power CMOS circuits

✍ Dee-Gwan Kang; Young June Park; Hong Shick Min 📂 Article 📅 1999 🏛 IEEE 🌐 English ⚖ 140 KB

Standby power consumption estimation by

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

✍ Paulo F. Butzen; Leomar S. da Rosa Jr; Erasmo J.D. Chiappetta Filho; André I. Re 📂 Article 📅 2010 🏛 Elsevier Science 🌐 English ⚖ 797 KB

Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, no

Design of low-power quaternary CMOS logi

Design of low-power quaternary CMOS logic circuits

✍ Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 📂 Article 📅 1986 🏛 John Wiley and Sons 🌐 English ⚖ 641 KB