𝔖 Bobbio Scriptorium

✦ LIBER ✦

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process

✍ Scribed by Ming-Dou Ker; Kuo-Chun Hsu

Book ID: 114616998
Publisher: IEEE
Year: 2003
Tongue: English
Weight: 608 KB
Volume: 50
Category: Article
ISSN: 0018-9383
DOI: 10.1109/ted.2003.809028

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

SCR device with dynamic holding voltage

SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-μm fully salicided CMOS process

✍ Ming-Dou Ker; Zi-Ping Chen 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 128 KB

Substrate-triggered technique for on-chi

Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process

✍ Ming-Dou Ker; Tung-Yang Chen 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 788 KB

On-chip ESD protection design with subst

On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

✍ Ming-Dou Ker; Lin, K.-H.; Chien-Hui Chuang 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 760 KB

[IEEE Proceedings of the 11th Internatio

[IEEE Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 - Taiwan (5-8 July 2004)] Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743) - ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) in a 0.25-μm salicided CMOS process

✍ Ming-Dou Ker, ; Che-Hao Chuang, 📂 Article 📅 2004 🏛 IEEE ⚖ 275 KB