✦ LIBER ✦

Skew Management of NBTI Impacted Gated Clock Trees

✍ Scribed by Chakraborty, A.; Pan, D. Z.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Clock skew reduction in ASIC logic desig

✍ Balboni, A.; Costi, C.; Pellencin, M.; Quadrini, A.; Sciuto, D. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 336 KB

Synthesis of clock tree topologies to im

✍ Kourtev, I.S.; Friedman, E.G. 📂 Article 📅 1999 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 519 KB

Impacts of NBTI/PBTI on power gated SRAM

✍ Ping Huang 黄平, Zuo-cheng Xing 邢座程 📂 Article 📅 2013 🏛 Central South University 🌐 English ⚖ 995 KB

Impact of Thermal Gradients on Clock Ske

✍ Bota, S.A.; Rossello, J.L.; de Benito, C.; Keshavarzi, A.; Segura, J. 📂 Article 📅 2006 🏛 IEEE 🌐 English ⚖ 224 KB

Impacts of NBTI/PBTI and Contact Resista

✍ Hao-I Yang; Wei Hwang; Ching-Te Chuang 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 806 KB

Speeding up pipelined circuits through a

✍ Sathyamurthy, H.; Sapatnekar, S.S.; Fishburn, J.P. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 308 KB