✦ LIBER ✦
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
✍ Scribed by Sathyamurthy, H.; Sapatnekar, S.S.; Fishburn, J.P.
- Book ID
- 119778293
- Publisher
- IEEE
- Year
- 1998
- Tongue
- English
- Weight
- 308 KB
- Volume
- 17
- Category
- Article
- ISSN
- 0278-0070
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