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Clock skew reduction in ASIC logic design: a methodology for clock tree management

✍ Scribed by Balboni, A.; Costi, C.; Pellencin, M.; Quadrini, A.; Sciuto, D.

Book ID: 119778321
Publisher: IEEE
Year: 1998
Tongue: English
Weight: 336 KB
Volume: 17
Category: Article
ISSN: 0278-0070
DOI: 10.1109/43.703824

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