[IEEE Comput. Soc . Design, Automation and Test in Europe Conference and Exhibition - Paris, France (16-20 Feb. 2004)] Proceedings Design, Automation and Test in Europe Conference and Exhibition - A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation

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✍ Agrawal, A.; Jha, N.K. 📂 Article 📅 2004 🏛 IEEE Comput. Soc 🌐 English ⚖ 242 KB

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✍ Piguet, C.; Gautier, J.; Heer, C.; O'Connor, I.; Schlichtmann, U. 📂 Article 📅 2004 🏛 IEEE Comput. Soc 🌐 English ⚖ 401 KB

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✍ Bruschi, F.; Bombana, M. 📂 Article 📅 2004 🏛 IEEE Comput. Soc 🌐 English ⚖ 346 KB

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✍ Posadas, H.; Herrera, F.; Sanchez, P.; Villar, E.; Blasco, F. 📂 Article 📅 2004 🏛 IEEE Comput. Soc 🌐 English ⚖ 253 KB

[IEEE Comput. Soc Design, Automation and

✍ Rong Jiang, ; Chung-Ping Chen, C. 📂 Article 📅 2004 🏛 IEEE Comput. Soc 🌐 English ⚖ 299 KB

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✍ Burns, F.; Shang, D.; Koelmans, A.; Yakovlev, A. 📂 Article 📅 2004 🏛 IEEE Comput. Soc 🌐 English ⚖ 205 KB