[IEEE Comput. Soc . Design, Automation and Test in Europe Conference and Exhibition - Paris, France (16-20 Feb. 2004)] Proceedings Design, Automation and Test in Europe Conference and Exhibition - An asynchronous synthesis toolset using Verilog

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✍ Papaefstathiou, I.; Kornaros, G.; Zervos, N. 📂 Article 📅 2004 🏛 IEEE Comput. Soc 🌐 English ⚖ 256 KB