✦ LIBER ✦

Single-grain Si TFTs with ECR-PECVD gate SiO2

✍ Scribed by Ishihara, R.; Hiroshima, Y.; Abe, D.; van Dijk, B.D.; van der Wilt, P.C.; Higashi, S.; Inoue, S.; Shimoda, T.; Metselaar, J.W.; Beenakker, C.I.M.

Book ID: 114617363
Publisher: IEEE
Year: 2004
Tongue: English
Weight: 166 KB
Volume: 51
Category: Article
ISSN: 0018-9383
DOI: 10.1109/ted.2004.823326

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

a-SI TFTS with Stacked Gate Insulator of

a-SI TFTS with Stacked Gate Insulator of CVD-SiO2/PECVD-SiNx

✍ Kaichi Fukuda; Nobuki Ibaraki 📂 Article 📅 1993 🏛 John Wiley and Sons 🌐 English ⚖ 622 KB

Single-Grain Si TFTs and Circuits Inside

Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of SiO2

✍ Rana, V.; Ishihara, R.; Hiroshima, Y.; Inoue, S.; Shimoda, T.; Metselaar, W.; Be 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 399 KB

Low voltage operation a-Si:H thin film t

Low voltage operation a-Si:H thin film transistors with very thin PECVD a-SiO2 gate dielectric

✍ Guglielmo Fortunato; Luigi Mariucci; Carlo Reita; Piero Foglietti 📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 174 KB

Improved off-current and subthreshold sl

Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel

✍ Walker, P.M.; Mizuta, H.; Uno, S.; Furuta, Y.; Hasko, D.G. 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 477 KB

High quality SiO2 gate insulator suitabl

High quality SiO2 gate insulator suitable for poly-Si TFTs on plastic substrates employing inductively coupled plasma-chemical vapor deposition with N2O plasma treatment and excimer laser annealing

✍ Sang-Myeon Han; Moon-Young Shin; Joong-Hyun Park; Min-Koo Han 📂 Article 📅 2006 🏛 Elsevier Science 🌐 English ⚖ 331 KB