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Secure Scan: A Design-for-Test Architecture for Crypto Chips

✍ Scribed by Bo Yang; Kaijie Wu; Karri, R.


Book ID
117907617
Publisher
IEEE
Year
2006
Tongue
English
Weight
206 KB
Volume
25
Category
Article
ISSN
0278-0070

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πŸ“œ SIMILAR VOLUMES


A test methodology for finite state mach
✍ Hyoung B. Min; William A. Rogers πŸ“‚ Article πŸ“… 1992 πŸ› Springer US 🌐 English βš– 876 KB

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits