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Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration

✍ Scribed by Al-Yamani, A.; Devta-Prasanna, N.; Chmelar, E.; Grinchuk, M.; Gunda, A.

Book ID
117907796
Publisher
IEEE
Year
2007
Tongue
English
Weight
817 KB
Volume
26
Category
Article
ISSN
0278-0070

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## Abstract It is common to use ATPG of scan‐based design for high fault coverage in LSI testing. However, significant increases in test cost arise with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have ser