𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Reliability evaluation of logic circuits using probabilistic gate models

✍ Scribed by Jie Han; Hao Chen; Erin Boykin; José Fortes

Book ID
108210905
Publisher
Elsevier Science
Year
2011
Tongue
English
Weight
393 KB
Volume
51
Category
Article
ISSN
0026-2714

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Signal probability for reliability evalu
Signal probability for reliability evaluation of logic circuits
✍ Franco, Denis Teixeira; Vasconcelos, Maí Correia; Naviner, Lirida; Naviner, Jea 📂 Article 📅 2008 🏛 Elsevier Science 🌐 English ⚖ 278 KB

As integrated circuits scale down into nanometer dimensions, a great reduction on the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate