Signal probability for reliability evaluation of logic circuits

✍ Scribed by Franco, Denis Teixeira; Vasconcelos, Maí Correia; Naviner, Lirida; Naviner, Jean-François

• Publisher: Elsevier Science
• Year: 2008
• Tongue: English
• Weight: 278 KB
• Volume: 48
• Category: Article
• ISSN: 0026-2714
• DOI: 10.1016/j.microrel.2008.07.002

✦ Synopsis

As integrated circuits scale down into nanometer dimensions, a great reduction on the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit's signal reliability as a function of its logical masking capabilities, concerning multiple simultaneous faults occurrence.