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Recursion and Testing of Combinational Circuits

โœ Scribed by Turcat, C.; Verdillon, A.


Book ID
114605892
Publisher
IEEE
Year
1976
Tongue
English
Weight
634 KB
Volume
C-25
Category
Article
ISSN
0018-9340

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A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF descri