✦ LIBER ✦

Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits

✍ Scribed by Kang-Sub Kwak, ; Oh-Kyong Kwon,

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 4-Gb/s CMOS clock and data recovery ci

✍ Seong-Jun Song; Sung Min Park; Hoi-Jun Yoo 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 573 KB

A power and area efficient CMOS clock/da

✍ Dao-Long Chen 📂 Article 📅 1996 🏛 IEEE 🌐 English ⚖ 982 KB

A monolithic 156 Mb/s clock and data rec

✍ Ishihara, N.; Akazawa, Y. 📂 Article 📅 1994 🏛 IEEE 🌐 English ⚖ 603 KB

PLL design technique by a loop-trajector

✍ Kishine, K.; Fujimoto, K.; Kusanagi, S.; Ichino, H. 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 568 KB

[IEEE IEEE Custom Integrated Circuits Co

✍ Yu, Hong; Bashirullah, Rizwan 📂 Article 📅 2006 🏛 IEEE 🌐 English ⚖ 551 KB

An electronic digital clock using integr

📂 Article 📅 1975 🏛 Elsevier Science 🌐 English ⚖ 251 KB