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PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits
✍ Scribed by Kishine, K.; Fujimoto, K.; Kusanagi, S.; Ichino, H.
- Book ID
- 119799340
- Publisher
- IEEE
- Year
- 2004
- Tongue
- English
- Weight
- 568 KB
- Volume
- 39
- Category
- Article
- ISSN
- 0018-9200
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