Planarization of dielectrics used in the manufacture of very-large-scale integrated circuits
β Scribed by Farid Malik; Raj Solanki
- Book ID
- 113204993
- Publisher
- Elsevier Science
- Year
- 1990
- Tongue
- English
- Weight
- 381 KB
- Volume
- 193-194
- Category
- Article
- ISSN
- 0040-6090
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
Mechanical polishing (MP) is a key technology for fabricating multi-layer, large-scale integrated Nb SFQ circuits. This process, however, could possibly influence junction characteristics. We studied the impact of a planarization process based on MP on the junction characteristics. The process, perf
Al-SI-Cu films deposIted on substrates of SI, borophosphate silicate glass and TiW mth improved electrical properties (lower sheet resistance) and rehatnhty (lugher Al[lll] diffraction mtensity) obtained by the proposed metalbzatlon process are described A chemometrx approach of umfymg the expernnen