✦ LIBER ✦

On variable clock methods for path delay testing of sequential circuits

✍ Scribed by Chakraborty, T.J.; Agrawal, V.D.; Bushnell, M.L.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

The optimistic update theorem for path d

✍ Soumitra Bose; Prathima Agrawal; Vishwani D. Agrawal 📂 Article 📅 1993 🏛 Springer US 🌐 English ⚖ 501 KB

Input Necessary Assignments for Testing

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 245 KB

Simulator for path-delay faults on mixed

✍ Yim, Y.T.; Kang, Y.S.; Kang, S. 📂 Article 📅 1997 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 703 KB

A simulator for at-speed robust testing

✍ Yuan-Chieh Hsu; Gupta, S.K. 📂 Article 📅 1996 🏛 IEEE 🌐 English ⚖ 937 KB

Combining GAs and Symbolic Methods for H

✍ Martin Keim; Nicole Drechsler; Rolf Drechsler; Bernd Becker 📂 Article 📅 2001 🏛 Springer US 🌐 English ⚖ 180 KB

A Method for Reducing the Number of Inpu

📂 Article 📅 1975 🏛 IEEE 🌐 English ⚖ 537 KB