Multi-Net Optimization of VLSI Interconnect

✍ Scribed by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer (auth.)

• Publisher: Springer-Verlag New York
• Year: 2015
• Tongue: English
• Leaves: 245
• Edition: 1
• Category: Library

✦ Synopsis

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.

✦ Table of Contents

Front Matter....Pages i-xvi
An Overview of the VLSI Interconnect Problem....Pages 1-9
Interconnect Aspects in Design Methodology and EDA Tools....Pages 11-16
Scaling Dependent Electrical Modeling of Interconnects....Pages 17-34
Frameworks for Interconnect Optimization....Pages 35-42
Net-by-Net Wire Optimization....Pages 43-61
Multi-net Sizing and Spacing of Bundle Wires....Pages 63-106
Multi-net Sizing and Spacing in General Layouts....Pages 107-165
Interconnect Optimization by Net Ordering....Pages 167-194
Layout Migration....Pages 195-219
Future Directions in Interconnect Optimization....Pages 221-222
Back Matter....Pages 223-233

✦ Subjects

Circuits and Systems; Electronics and Microelectronics, Instrumentation; Processor Architectures