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Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

✍ Scribed by Afzalian, A.; Flandre, D.


Book ID
114616935
Publisher
IEEE
Year
2003
Tongue
English
Weight
357 KB
Volume
50
Category
Article
ISSN
0018-9383

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This paper presents an analog design methodology, using the selection of inversion coefficient of MOS devices, to design lowvoltage and low-power (LVLP) CMOS voltage references. These circuits often work under subthreshold operation. Hence, there is a demand for analog design methods that optimize t