[ACM Press the 23rd symposium - São Paulo, Brazil (2010.09.06-2010.09.09)] Proceedings of the 23rd symposium on Integrated circuits and system design - SBCCI '10 - Design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference

✍ Scribed by Colombo, Dalton Martini; Wirth, Gilson Inacio; Fayomi, Christian

• Book ID: 121688383
• Publisher: ACM Press
• Year: 2010
• Weight: 678 KB
• Category: Article
• ISBN: 1450301525
• DOI: 10.1145/1854153.1854166

✦ Synopsis

This paper presents an analog design methodology, using the selection of inversion coefficient of MOS devices, to design lowvoltage and low-power (LVLP) CMOS voltage references. These circuits often work under subthreshold operation. Hence, there is a demand for analog design methods that optimize the sizing process of transistors working in weak and moderate inversion. The advantage of the presented method -compared with the traditional approach to design circuits -is the reduction of design cycle time and minimization of trial-and-error simulations, if the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with supply voltage of 0.7 V was designed for 0.18-µm CMOS technology.