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Mixed Full Adder topologies for high-performance low-power arithmetic circuits

✍ Scribed by M. Alioto; G. Di Cataldo; G. Palumbo

Publisher: Elsevier Science
Year: 2007
Tongue: English
Weight: 217 KB
Volume: 38
Category: Article
ISSN: 0026-2692
DOI: 10.1016/j.mejo.2006.09.001

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