Low power multipliers based on new hybrid full adders

✍ Scribed by Z. Abid; H. El-Razouk; D.A. El-Dib

• Publisher: Elsevier Science
• Year: 2008
• Tongue: English
• Weight: 398 KB
• Volume: 39
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/j.mejo.2008.04.002

✦ Synopsis

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8 Â 8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.