Integrated inductors on porous silicon

✍ Scribed by Contopanagos, H. ;Nassiopoulou, A. G.

• Book ID: 105364961
• Publisher: John Wiley and Sons
• Year: 2007
• Tongue: English
• Weight: 400 KB
• Volume: 204
• Category: Article
• ISSN: 0031-8965
• DOI: 10.1002/pssa.200790009

✦ Synopsis

Abstract

The cover picture illustrates the effective use of a thick porous silicon layer as an integrated micro‐plate for RF isolation on a silicon substrate, proposed by Harry Contopanagos and Androula Nassiopoulou in their Original Paper [1] in the current issue. What is plotted is the magnitude of the current distribution (colour coded from blue (low) to high (red) values) on the metallization and on a screen 50 µm underneath the bottom oxide layer of a 2‐metal integrated CMOS‐compatible inductor on bulk silicon (lower right) and on a 50 µm thick porous silicon layer (upper left) for a frequency of 2.5 GHz.

Inductors were designed in a standard 0.13 µm CMOS technology. Efficient RF isolation is produced by the porous Si layer, as evidenced by the virtual elimination of surface currents relative to the case of standard CMOS, indicating virtually complete substrate shielding by a 50 µm thick porous Si layer for the relevant size scale. The quality factor of the inductor with the use of the porous Si layer is increased by 100%, reaching a maximum value of 33 for the design shown.

The first author of the article is a visiting senior researcher at the Institute of Microelectronics (IMEL), National Center for Scientific Research “Demokritos” (Athens, Greece). His research focuses on electromagnetics and microwave engineering, artificial materials and photonic crystals, wireless front ends, antennas and high‐frequency analog integrated circuits.