## Abstract We examine porous Si as a thick RF‐isolation layer for on‐chip inductors and separate the loss sources that downgrade the __Q__ factors into their material components, namely Si substrate loss and metal types common to standard CMOS technologies. First we validate theoretical designs wi
✦ LIBER ✦
Fabrication, characterisation and modelling of integrated on-silicon inductors
✍ Scribed by R. Murphy-Arteaga; J. Huerta-Chua; A. Dı́az-Sánchez; A. Torres-Jacome; W. Calleja-Arriaga; M. Landa-Vázquez
- Book ID
- 108361944
- Publisher
- Elsevier Science
- Year
- 2003
- Tongue
- English
- Weight
- 231 KB
- Volume
- 43
- Category
- Article
- ISSN
- 0026-2714
No coin nor oath required. For personal study only.
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## Abstract The cover picture illustrates the effective use of a thick porous silicon layer as an integrated micro‐plate for RF isolation on a silicon substrate, proposed by Harry Contopanagos and Androula Nassiopoulou in their Original Paper [1] in the current issue. What is plotted is the magnitu
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