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Impact of on-chip network parameters on nuca cache performances

✍ Scribed by Bardine, A.; Comparetti, M.; Foglia, P.; Gabrielli, G.; Prete, C.A.

Book ID
117809854
Publisher
The Institution of Engineering and Technology
Year
2009
Tongue
English
Weight
573 KB
Volume
3
Category
Article
ISSN
1751-8601

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## Abstract Recent semiconductor technology has made on‐chip multiprocessors with several CPUs and cache memories on a single chip a realistic possibility. Generally, conventional multiprocessor systems with shared memory offer a simple programming model, but need a cache coherency mechanism that m