Chip size and performance evaluations of shared cache for on-chip multiprocessor

✍ Scribed by Takahiro Sasaki; Tomohiro Inoue; Nobuhiko Omori; Tetsuo Hironaka; Hans J. Mattausch; Tetsushi Koide

• Publisher: John Wiley and Sons
• Year: 2005
• Tongue: English
• Weight: 377 KB
• Volume: 36
• Category: Article
• ISSN: 0882-1666
• DOI: 10.1002/scj.20244

✦ Synopsis

Abstract

Recent semiconductor technology has made on‐chip multiprocessors with several CPUs and cache memories on a single chip a realistic possibility. Generally, conventional multiprocessor systems with shared memory offer a simple programming model, but need a cache coherency mechanism that may become a system bottleneck. Furthermore, the same data may be cached on two or more caches, which prevents effective cache utilization. The multiport cache is one solution, but when using the conventional multiport memory architecture, the chip size of the multiport cache will increase in proportion to the square of the number of ports. On the other hand, with our proposed hierarchical multiport memory architecture, multiport memory can be implemented with a smaller chip size than by the conventional methods. This paper proposes the shared cache with a hierarchical multiport memory architecture that does not need a coherency mechanism. This paper also presents the results of performance evaluations and chip size estimations. © 2005 Wiley Periodicals, Inc. Syst Comp Jpn, 36(9): 1–13, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20244