✦ LIBER ✦

Impact of line-edge roughness on resistance and capacitance of scaled interconnects

✍ Scribed by M. Stucchi; M. Bamal; K. Maex

Publisher: Elsevier Science
Year: 2007
Tongue: English
Weight: 1003 KB
Volume: 84
Category: Article
ISSN: 0167-9317
DOI: 10.1016/j.mee.2007.05.038

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✦ Synopsis

The impact of line-edge roughness (LER) on resistance R and capacitance C of on-chip interconnects is for the first time evaluated by a simulation methodology based on a realistic modeling of LER. The model can be calibrated with measured LER parameters. A geometrical approximations of LER is generated and superimposed to an interconnect architecture model with no roughness; resistance and capacitance are extracted from the model by a 3D static solver to estimate the impact of LER on them. By applying this methodology to the interconnect scaling scenario of the 2005 ITRS Roadmap, a small but increasing detrimental effect of LER on both R and C is predicted.

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