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[IEEE IEEE 2000 International Interconnect Technology Conference - Burlingame, CA, USA (5-7 June 2000)] Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407) - When should on-chip inductance modeling become necessary for VLSI timing analysis?

✍ Scribed by Li-Fu Chang, ; Keh-Jeng Chang, ; Mathews, R.

Book ID: 126677532
Publisher: IEEE
Year: 2000
Weight: 286 KB
Category: Article
ISBN-13: 9780780363274
DOI: 10.1109/IITC.2000.854315

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