[IEEE Comput. Soc. Press IEEE International Workshop on Memory Technology, Design, and Test - San Jose, CA, USA (8-9 Aug. 1994)] Proceedings of IEEE International Workshop on Memory Technology, Design, and Test - Design of an active memory system for network applications

[IEEE Comput. Soc. Press IEEE Internatio

[IEEE Comput. Soc. Press IEEE International Workshop on Memory Technology, Design, and Test - San Jose, CA, USA (8-9 Aug. 1994)] Proceedings of IEEE International Workshop on Memory Technology, Design, and Test - Using sinusoidal stimuli and Fourier analyses for memory IC testing

✍ Thibeault, C. 📂 Article 📅 1994 🏛 IEEE Comput. Soc. Press ⚖ 470 KB

[IEEE Comput. Soc. Press IEEE Internatio

[IEEE Comput. Soc. Press IEEE International Workshop on Memory Technology, Design, and Test - San Jose, CA, USA (8-9 Aug. 1994)] Proceedings of IEEE International Workshop on Memory Technology, Design, and Test - Built-in random testing for dual-port RAMs

✍ Yokoyama, H.; Tamamoto, H.; Xiaoqing Wen, 📂 Article 📅 1994 🏛 IEEE Comput. Soc. Press ⚖ 399 KB

[IEEE Comput. Soc. Press IEEE Internatio

[IEEE Comput. Soc. Press IEEE International Workshop on Memory Technology, Design, and Test - San Jose, CA, USA (8-9 Aug. 1994)] Proceedings of IEEE International Workshop on Memory Technology, Design, and Test - GOS defects in SRAM: fault modeling and testing possibilities

✍ Segura, J.A.; Rubio, A. 📂 Article 📅 1994 🏛 IEEE Comput. Soc. Press ⚖ 444 KB

[IEEE Comput. Soc. Press IEEE Internatio

[IEEE Comput. Soc. Press IEEE International Workshop on Memory Technology, Design, and Test - San Jose, CA, USA (8-9 Aug. 1994)] Proceedings of IEEE International Workshop on Memory Technology, Design, and Test - Mechanical stress induced void and hillock formations in thin films

✍ Lahiri, S.K. 📂 Article 📅 1994 🏛 IEEE Comput. Soc. Press ⚖ 521 KB

[IEEE Comput. Soc. Press Records of the

[IEEE Comput. Soc. Press Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (7-8 Aug. 1995)] Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing - Modeling application specific memories

✍ Das, D.V.; Kumar, R.; Lauria, M. 📂 Article 📅 1995 🏛 IEEE Comput. Soc. Press ⚖ 327 KB

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Workshop on Memory Technology, Design and Testing - San Jose, CA, USA (6-7 Aug. 2001)] Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing - An error control code scheme for multilevel Flash memories

✍ Gregori, S.; Khouri, O.; Micheloni, R.; Torelli, G. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 365 KB

The 14 papers in this collection from the August 2001 workshop are divided into five sessions on semiconductor memory design, BIST, redundancy and error control, fault models and multi-port SRAM testing, and verification and testing. Some of the topics are evaluation of redundancy analysis algorithm