𝔖 Bobbio Scriptorium

✦ LIBER ✦

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding

✍ Scribed by Pande, Partha; Ganguly, Amlan; Feero, Brett; Belzer, Benjamin; Grecu, Cristian

Book ID: 118146370
Publisher: IEEE
Year: 2006
Weight: 273 KB
Volume: 0
Category: Article
ISBN-13: 9780769527062
DOI: 10.1109/dft.2006.22

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

[IEEE 2006 21st IEEE International Sympo

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - VLSI Implementation of a Fault-Tolerant Distributed Clock Generation

✍ Ferringer, M.; Fuchs, G.; Steininger, A.; Kempf, G. 📂 Article 📅 2006 🏛 IEEE ⚖ 248 KB

[IEEE 2006 21st IEEE International Sympo

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Reliability Evaluation of Repairable/Reconfigurable FPGAs

✍ Pontarelli, S.; Ottavi, M.; Vankamamidi, V.; Salsano, A.; Lombardi, F. 📂 Article 📅 2006 🏛 IEEE ⚖ 191 KB

[IEEE 2006 21st IEEE International Sympo

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - SET Fault Tolerant Combinational Circuits Based on Majority Logic

✍ Michels, A.; Petroli, L.; Lisboa, C.A.L.; Kastensmidt, F.; Carro, L. 📂 Article 📅 2006 🏛 IEEE ⚖ 143 KB

[IEEE 2006 21st IEEE International Sympo

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Adaptive Design for Performance-Optimized Robustness

✍ Datta, Ramyanshu; Abraham, Jacob; Diril, Abdulkadir; Chatterjee, Abhijit; Nowka, 📂 Article 📅 2006 🏛 IEEE ⚖ 166 KB

[IEEE 2006 21st IEEE International Sympo

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Synthesis of Efficient Linear Test Pattern Generators

✍ Dutta, Avijit; Touba, Nur 📂 Article 📅 2006 🏛 IEEE ⚖ 285 KB

[IEEE 2006 21st IEEE International Sympo

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Scan-Based Delay Fault Tests for Diagnosis of Transition Faults

✍ Pomeranz, Irith; Reddy, Sudhakar 📂 Article 📅 2006 🏛 IEEE ⚖ 131 KB