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Identifying invalid states for sequential circuit test generation

✍ Scribed by Hsing-Chung Liang; Chung Len Lee; Chen, J.E.


Book ID
119778231
Publisher
IEEE
Year
1997
Tongue
English
Weight
224 KB
Volume
16
Category
Article
ISSN
0278-0070

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Sequential circuit test generation by re
✍ Kazunori Hikone; Mitsuji Ikeda; Kazumi Hatayama; Terumine Hayashi πŸ“‚ Article πŸ“… 1993 πŸ› John Wiley and Sons 🌐 English βš– 921 KB

## Abstract This paper presents a test generation method using an optimization technique for a single stuck‐at fault in synchronous sequential circuits. This method utilizes a new real number simulation for defining the cost of an input pattern for a given fault and leads an input pattern to a test