<p>This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis
Digital Logic Design Using Verilog: Coding and RTL Synthesis
โ Scribed by Vaibbhav Taraate (auth.)
- Publisher
- Springer India
- Year
- 2016
- Tongue
- English
- Leaves
- 431
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Synopsis
This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.
โฆ Table of Contents
Front Matter....Pages i-xxiii
Introduction....Pages 1-26
Combinational Logic Design (Part I)....Pages 27-52
Combinational Logic Design (Part II)....Pages 53-78
Combinational Design Guidelines....Pages 79-102
Sequential Logic Design....Pages 103-144
Sequential Design Guidelines....Pages 145-169
Complex Designs Using Verilog RTL....Pages 171-196
Finite State Machines....Pages 197-217
Simulation Concepts and PLD-Based Designs....Pages 219-253
ASIC RTL Synthesis....Pages 255-275
Static Timing Analysis....Pages 277-298
Constraining ASIC Design....Pages 299-320
Multiple Clock Domain Design....Pages 321-358
Low Power Design....Pages 359-380
System on Chip (SOC) Design....Pages 381-398
Back Matter....Pages 399-416
โฆ Subjects
Circuits and Systems; Electronics and Microelectronics, Instrumentation; Logic Design
๐ SIMILAR VOLUMES
<p>This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integ
<p></p><p><span>This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book c
Provides a practical approach to Verilog design and problem solving. * Bulk of the book deals with practical design problems that design engineers solve on a daily basis. * Includes over 90 design examples. * There are 3 full scale design examples that include specification, architectura