Preface
Acknowledgements
Contents
About the Author
1 Introduction
1.1 ASIC Design
1.2 Types of ASIC
1.3 Abstraction Levels
1.4 Design Examples
1.5 What We Should Know?
1.6 Important Terms Used Throughout Design Cycle
1.7 Chapter Summary
2 ASIC Design Flow
2.1 ASIC Design Flow
2.1.1 Logic Design
2.1.2 Physical Design
2.2 FPGA Design Flow
2.3 Examples and Thought Process
2.4 Design Challenges
2.5 Chapter Summary
3 Let Us Build Design Foundation
3.1 Combinational Design Elements
3.2 Logic Understanding and Use of Construct
3.3 Arithmetic Resources and Area
3.4 Code Converter
3.4.1 Binary to Gray Code Converter
3.4.2 Gray to Binary Code Converter
3.5 Multiplexers
3.6 Cascading Stages of MUX Using Instantiation
3.7 Decoders
3.8 Encoders
3.9 Priority Encoders
3.10 Strategies During ASIC Design
3.11 Exercises
3.12 Chapter Summary
4 Sequential Design Concepts
4.1 Sequential Design Elements
4.2 Let Us Understand Blocking Versus Non-blocking Assignments
4.2.1 Blocking Assignments
4.2.2 Reordering of the Blocking Assignments
4.2.3 Non-blocking Assignments
4.2.4 Reordering of the Non-blocking Assignments
4.3 Latch-Based Designs
4.4 Flip-Flop-Based Designs
4.5 Reset Strategies
4.5.1 Asynchronous Reset
4.5.2 Synchronous Reset
4.6 Frequency Divider
4.7 Synchronous Design
4.8 Asynchronous Design
4.9 RTL Design and Verification for Complex Designs
4.10 Exercises
4.11 Chapter Summary
5 Important Design Considerations
5.1 Timing Parameters
5.2 Metastability
5.3 Clock Skew
5.3.1 Positive Clock Skew
5.3.2 Negative Clock Skew
5.4 Slack
5.4.1 Setup Slack
5.4.2 Hold Slack
5.5 Clock Latency
5.6 Area for the Design
5.7 Speed Requirements
5.8 Power Requirements
5.9 What Are Design Constraints?
5.10 Exercises
5.11 Chapter Summary
6 Important Considerations for ASIC Designs
6.1 Synchronous Design and Considerations
6.2 Positive Clock Skew and Impact on Speed
6.3 Negative Clock Skew and Impact on the Speed
6.4 Clock and Network Latency
6.5 Timing Paths in the Design
6.5.1 Input to Reg Path
6.5.2 Reg to Output Path
6.5.3 Reg to Reg Path
6.5.4 Input to Output Path
6.6 Frequency Calculations
6.7 What Is On-Chip Variations
6.8 Exercises
6.9 Chapter Summary
7 Multiple Clock Domain Designs
7.1 General Strategies for Multiple Clock Domain Designs
7.2 What Are Issues in the Multiple Clock Domain Design
7.3 Architecture Design Strategies
7.4 Control Path and Synchronization
7.4.1 Level or Multiflop Synchronizer
7.4.2 Pulse Synchronizers
7.4.3 MUX Synchronizer
7.5 Challenges in the Multiple Bit Data Transfer
7.6 Data Path Synchronizers
7.6.1 Handshaking Mechanism
7.6.2 FIFO Synchronizer
7.6.3 Gray Encoding
7.7 Summary and Future Discussions
8 Low Power Design Considerations
8.1 Introduction to Low Power Design
8.2 Sources of Power
8.3 Power Optimization During the RTL Design
8.4 Switching and Leakage Power Reduction Techniques
8.4.1 Clock Gating and Clock Tree Optimizations
8.4.2 Operand Isolations
8.4.3 Multiple Vth
8.4.4 Multiple Supply Voltages (MSV)
8.4.5 Dynamic Voltage and Frequency Scaling (DVSF)
8.4.6 Power Gating (Power Shut Off)
8.4.7 Isolation Logic
8.4.8 State Retention
8.5 Low-Power Design Architecture and Use of UPF
8.6 Chapter Summary
9 Architecture and Micro-architecture Design
9.1 Architecture Design
9.2 Micro-architecture Design
9.3 Use of Document During Various Design Phases
9.4 Design Partitioning
9.5 Multiple Clock Domains and Clock Grouping
9.6 Architecture Tweaking and Performance Improvement
9.7 Strategies for the Micro-architecture Design of Processor
9.8 Chapter Summary
10 Design Constraints and SDC Commands
10.1 Important Design Concepts
10.1.1 Clock Tree
10.1.2 Reset Tree
10.1.3 Clock and Reset Strategies
10.1.4 What Impacts on Design Performance?
10.2 How to Interpret the Constraints
10.2.1 Area Constraints
10.2.2 Speed Constraints
10.2.3 Power Constraints
10.3 Issues in the Design
10.4 Important SDC Commands Used During Synthesis
10.4.1 Synopsys DC Commands
10.4.2 Checking of the Design
10.4.3 Clock Definitions
10.4.4 Skew Definition
10.4.5 Defining Input and Output Delay
10.4.6 Specifying the Minimum (min) and Maximum (max) Delay
10.4.7 Design Synthesis
10.4.8 Save the Design
10.5 Constraint Validation
10.6 Commands for the DRC, Power, and Optimization
10.7 Chapter Summary
11 Design Synthesis and Optimization Using RTL Tweaks
11.1 ASIC Synthesis
11.2 Synthesis Guidelines
11.3 FSM Design and Synthesis
11.4 Strategies for the Complex FSM Controllers
11.5 How RTL Tweaks Are Useful During Synthesis?
11.6 Synthesis Optimization Techniques Using RTL Tweaks
11.6.1 Resource Allocation
11.6.2 Dead Zone Elimination
11.6.3 Use of Parentheses
11.6.4 Grouping the Terms
11.7 FPGA Synthesis
11.8 Chapter Summary
12 Synthesis and Optimization Techniques
12.1 Introduction
12.2 Synthesis Using Design Compiler
12.3 Synthesis and Optimization Flow
12.4 Area Optimization Techniques
12.4.1 Avoid Use of Combinational Logic as Individual Block
12.4.2 Avoid Use of Glue Logic Between Two Modules
12.4.3 Use of setmaxarea Attribute
12.4.4 Area Report
12.5 Design Partitioning and Structuring
12.6 Compilation Strategy
12.6.1 Top-Down Compilation
12.6.2 Bottom-Up Compilation
12.7 Chapter Summary
13 Design Optimization and Scenarios
13.1 Design Rule Constraints (DRC)
13.1.1 maxfanout
13.1.2 maxtransition
13.1.3 maxcapacitance
13.2 Clock Definitions and Latency
13.2.1 Clock Network Latency
13.2.2 Generated Clock
13.2.3 Clock Muxing and False Paths
13.2.4 Clock Gating
13.3 Commands Useful During Design Synthesis and Optimization
13.3.1 setdontuse
13.3.2 setdonttouch
13.3.3 setprefer
13.3.4 Command for the Design Flattening
13.3.5 Commands Used for Structuring
13.3.6 Group and Ungroup Commands
13.4 Timing Optimization and Performance Improvement
13.4.1 Design Compilation with âmapeffort highâ
13.4.2 Logical Flattening
13.4.3 Use of grouppath Command
13.4.4 Submodule Characterizing
13.4.5 Register Balancing
13.5 FSM Optimization
13.6 Fixing Hold Violations
13.7 Report Command
13.7.1 reportqor
13.7.2 reportconstraints
13.7.3 reportcontraintsall
13.8 Multicycle Paths
13.9 Chapter Summary
14 Design for Testability
14.1 What Is Need of DFT?
14.2 Testing for Faults in the Design
14.3 Testing
14.4 Strategies Used During the DFT
14.5 Scan Methods
14.5.1 Mux-Based Scan
14.5.2 Boundary Scan
14.5.3 Built-In Self-Test (BIST)
14.6 Scan Insertion
14.7 Challenges During the DFT
14.8 DFT Flow and Test Compiler Commands
14.9 The Scan Design Rules to Avoid DRC Violations
14.10 Chapter Summary
15 Timing Analysis
15.1 Introduction
15.2 What Are Timing Paths for Design
15.2.1 Input to Reg Path
15.2.2 Reg to Output Path
15.2.3 Reg to Reg Path
15.2.4 Input to Output Path
15.3 Let Us Specify the Timing Goals
15.4 Timing Reports
15.5 Strategies to Fix Timing Violations
15.5.1 Fixing Setup Violations in the Design
15.5.2 Hold Violation Fix
15.5.3 Timing Exceptions
15.6 Chapter Summary
16 Physical Design
16.1 Physical Design Flow
16.2 Foundation and Important Terms
16.3 Floor Planning and Power Planning
16.4 Power Planning
16.5 Clock Tree Synthesis
16.6 Place and Route
16.7 Routing
16.8 Back Annotation
16.9 Signoff STA and Layout
16.10 Chapter Summary
Reference
17 Case Study: Processor ASIC Implementation
17.1 Functional Understanding
17.2 Strategies During Architecture Design
17.3 Micro-architecture Strategies
17.4 Strategies During RTL Design and Verification
17.5 The Sample Script Used During Synthesis
17.6 Synthesis Issues and Fixes
17.7 Pre-layout STA Issues
17.8 Physical Design Issues
17.9 Chapter Summary
18 Programmable ASIC
18.1 Programmable ASIC
18.2 Design Flow
18.3 Modern FPGA Fabric and Elements
18.4 RTL Design and Verification
18.5 FPGA Synthesis
18.5.1 Arithmetic Operators and Synthesis
18.5.2 Relational Operator and Synthesis
18.5.3 Equality Operator Synthesis
18.6 Design at Fabric Level
18.7 Chapter Summary
19 Prototyping Design
19.1 FPGAs for Prototyping
19.2 Synthesis Strategies During Prototyping
19.2.1 Fast Synthesis for Initial Resource Estimation
19.2.2 Incremental Synthesis
19.3 Constraints During FPGA Synthesis
19.4 Important Considerations and Tweaks
19.5 IO Pad Synthesis for FPGA
19.6 Prototyping Tools
19.7 Chapter Summary
20 Case Study: IP Design and Development
20.1 IP Design and Development
20.2 What We Consider During the IP Selection
20.3 Strategies Useful During the IP Design
20.4 Prototyping Using Multiple FPGA
20.5 H.264. Encoder IP Design and Development
20.5.1 Features and Micro-architecture Design Strategies
20.5.2 Strategies During RTL Design and Verification
20.5.3 Strategies During Synthesis and DFT
20.5.4 Strategies During Pre-layout STA
20.5.5 Strategies During Physical Design
20.6 ULSI and ASIC Design
20.7 Chapter Summary
Appendix A
Appendix B
Bibliography
Index