Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog

✍ Scribed by Vaibbhav Taraate

Publisher: Springer Singapore
Year: 2019
Tongue: English
Leaves: 319
Edition: 1st ed.
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

✦ Table of Contents

Front Matter ....Pages i-xxi
Introduction (Vaibbhav Taraate)....Pages 1-16
SOC Design (Vaibbhav Taraate)....Pages 17-24
RTL Design Guidelines (Vaibbhav Taraate)....Pages 25-50
RTL Design and Verification (Vaibbhav Taraate)....Pages 51-62
Processor Cores and Architecture Design (Vaibbhav Taraate)....Pages 63-95
Buses and Protocols in SOC Designs (Vaibbhav Taraate)....Pages 97-117
Memory and Memory Controllers (Vaibbhav Taraate)....Pages 119-139
DSP Algorithms and Video Processing (Vaibbhav Taraate)....Pages 141-158
ASIC and FPGA Synthesis (Vaibbhav Taraate)....Pages 159-172
Static Timing Analysis (Vaibbhav Taraate)....Pages 173-196
SOC Prototyping (Vaibbhav Taraate)....Pages 197-210
SOC Prototyping Guidelines (Vaibbhav Taraate)....Pages 211-230
Design Integration and SOC Synthesis (Vaibbhav Taraate)....Pages 231-245
Interconnect Delays and Timing (Vaibbhav Taraate)....Pages 247-262
SOC Prototyping and Debug Techniques (Vaibbhav Taraate)....Pages 263-276
Testing at the Board Level (Vaibbhav Taraate)....Pages 277-290
Back Matter ....Pages 291-307

✦ Subjects

Engineering; Circuits and Systems; Control Structures and Microprogramming; Logic Design

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