Logic Synthesis and SOC Prototyping: RTL Design using VHDL

✍ Scribed by Vaibbhav Taraate

• Publisher: Springer
• Year: 2020
• Tongue: English
• Leaves: 260
• Category: Library

✦ Synopsis

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.

✦ Table of Contents

Preface
Acknowledgements
Contents
About the Author
1 Introduction
1.1 ASIC Design
1.1.1 Types of ASIC [3]
1.2 Design Challenges
1.3 ASIC Design Flow
1.4 Need of HDL?
1.5 Hardware Description Languages
1.6 Hardware Construction and IP Design
1.7 ASIC/SOC Design Challenges and Areas
1.8 Important Points to Conclude the Chapter
2 ASIC Design and SOC Prototyping
2.1 SOC Design
2.2 SOC Design Flow
2.2.1 Design Specifications and System Architecture
2.2.2 RTL Design and Functional Verification
2.2.3 Synthesis and Timing Verification
2.2.4 Physical Design and Verification
2.2.5 Prototype and Test
2.3 SOC Prototyping and Challenges
2.4 ASIC Prototyping
2.5 Important Design Compiler (DC) Commands
2.6 Important Points to Conclude the Chapter
Reference
3 Design Using VHDL and Guidelines
3.1 RTL Design Guidelines
3.2 RTL Design Practical Scenarios
3.2.1 Incomplete Sensitivity List
3.2.2 Case Versus If-then-else
3.3 Grouping the Terms
3.4 Tristate Buses and Logic
3.5 Resource Sharing
3.6 Level Synchronizer
3.7 Gated Clocks
3.8 Clock Enables
3.9 Important Points to Conclude the Chapter
Reference
4 VHDL Design Scenarios and Synthesis
4.1 Multiple Clock Domain and Code Converters
4.1.1 Binary to Gray Code Converter
4.1.2 Gray to Binary Code Converter
4.2 Synthesis for Multiple Architecture
4.3 Signal Definition and Synthesis
4.4 Variable Assignment and Synthesis
4.5 Multiple Process Blocks and Synthesis
4.6 Synthesis for Nested If-then-else
4.7 Case Construct and Synthesis
4.8 Priority Logic Using Synthesizable Constructs
4.9 Synthesis of Parity Logic
4.10 Latch Based Design and Synthesis
4.11 PIPO Registers and Synthesis
4.12 Synthesis and Logic Inference of Shift Register
4.13 Edge Detection Logic and Synthesis
4.14 Important Points to Conclude the Chapter
Reference
5 Design and Verification Strategies
5.1 Design Strategies for Complex Designs
5.2 RTL Design Strategies for SOC
5.3 Processor Architecture Case Study [1]
5.4 Processor Architecture and Micro-architecture
5.4.1 Processor Micro-architecture
5.5 RTL Top-Level Design and Synthesis [1]
5.5.1 Block-Level Design
5.5.2 Top-Level Design
5.6 Strategies for SOC Verification
5.7 Important Points to Conclude the Chapter
Reference
6 VHDL Design and RTL Tweaks
6.1 Reset Strategies
6.1.1 Asynchronous Reset
6.1.2 Synchronous Reset
6.2 State Machines
6.2.1 Moore Machine
6.2.2 Mealy Machine
6.3 RTL Design of Moore Machine
6.4 RTL Design of Mealy Machine
6.5 FSM Synthesis and Optimization
6.6 Data Transfer and Arbiter Design
6.6.1 Bus Arbitration
6.7 DSP-Based Designs and RTL Strategies
6.8 Recommended RTL Tweaks
6.9 Important Points to Conclude the Chapter
Reference
7 ASIC Synthesis and Design Constraints
7.1 Design Partitioning for Complex Designs
7.2 ASIC Synthesis
7.3 Synthesis Using Design Compiler (DC)
7.4 DC Commands Used During Synthesis
7.4.1 DC Commands to Read the Design
7.4.2 DC Commands to Check the Design
7.4.3 DC Commands to Define Skew
7.4.4 DC Commands to Specify Input and Output Delay
7.4.5 DC Commands to Specify Minimum (Min) and Maximum (Max) Delay
7.4.6 Command Used to Perform Synthesis
7.4.7 DC Command to Save the Design
7.5 Design Optimization Constraints and Basic Script
7.6 Clock Network Latency
7.7 Generated Clock
7.8 Clock Muxing and False Paths
7.9 Clock Gating
7.10 Multicycle Paths
7.11 Important Points to Conclude the Chapter
Reference
8 Design Optimization
8.1 ASIC Synthesis and Design Constraints
8.1.1 Block-Level Synthesis and Constraints
8.1.2 Chip-Level Synthesis and Constraints
8.2 Design Rule Constraints (DRC)
8.2.1 maxfanout
8.2.2 maxtransition
8.2.3 maxcapacitance
8.3 Optimization Constraints
8.3.1 setdontuse
8.3.2 setdonttouch
8.3.3 setprefer
8.3.4 Command for the Design Flattening
8.3.5 Commands Used for Structuring
8.3.6 Group and Ungroup Commands
8.4 FSM Optimization
8.5 Important Points to Conclude the Chapter
Reference
9 Design Optimization Scenarios
9.1 Where Is the Issue in Optimization?
9.2 Design Optimization Strategies for the SOC
9.3 Compilation Strategies
9.3.1 Top-Down Compilation
9.3.2 Bottom-up Compilation
9.4 Strategies for Area Optimization
9.4.1 Do not Use Combinational Logic as Individual Block
9.4.2 Do not Use Glue Logic Between Two Modules
9.4.3 Use of setmaxarea Attribute
9.4.4 Area Report
9.5 Strategies for Timing Optimization and Performance Improvement
9.5.1 Design Compilation with ‘mapefforthigh’
9.5.2 Use of grouppath Command
9.5.3 Setup Time Analysis and Check
9.5.4 Hold Time Analysis and Check
9.5.5 Submodule Characterization
9.5.6 Register Balancing
9.5.7 Multicycle Paths
9.6 Important Points to Conclude the Chapter
References
10 FPGA for SOC Prototyping
10.1 Xilinx 7 Series FPGA
10.1.1 Xilinx 7 Series CLB Architecture
10.1.2 Xilinx 7 Series Block RAM
10.1.3 Xilinx 7 Series DSP
10.1.4 Xilinx 7 Series Clocking
10.1.5 XILINX 7 Series IO
10.1.6 Xilinx 7 Series Transceivers
10.1.7 In-Built IPs
10.1.8 Built-In Monitor
10.2 Synthesis and Implementation Flow [2]
10.2.1 How Logic Is Mapped Using CLBs?
10.2.2 How DSP Blocks Are Mapped?
10.2.3 How Memory Blocks Are Mapped Inside FPGA?
10.3 The Techniques for the Better Optimization
10.3.1 Multipliers and Resource Sharing
10.3.2 Logic Duplication for the Larger Decoding Logic
10.4 Strategies for SOC Prototyping
10.5 Important Points to Conclude the Chapter
References
11 Prototyping Using Single and Multiple FPGAs
11.1 Choosing the Target FPGA
11.2 SOC Prototyping Using Single FPGA
11.3 How to Reduce the Risk During the Prototyping?
11.4 Prototyping Using Multiple FPGAs
11.5 Deferred Interconnects
11.6 Onboard Delay Timing [1]
11.7 Strategies and Guidelines for the Efficient Prototyping
11.7.1 General Guidelines and Project Planning [1]
11.7.2 IO Planning and Strategies to Minimize Pin Count [1]
11.8 IO Planning and Constraints [1]
11.9 Important Points to Conclude the Chapter
References
12 SOC Design Synthesis and Implementation
12.1 Design Partitioning and Goals
12.2 Challenges in the Design Partitioning
12.3 How to Overcome the Partitioning Challenges [1]
12.3.1 Architecture Level
12.3.2 Synthesis at Netlist Level [1]
12.4 Need of the EDA Tools for the Design Partitioning [1]
12.4.1 Manual Partitioning
12.4.2 Automatic Partitioning
12.5 Synthesis for the Better Prototype Outcome [1]
12.5.1 Fast Synthesis for Initial Resource Estimation
12.5.2 Incremental Synthesis
12.6 Constraints and Synthesis for FPGA Designs [1]
12.7 IO Pad Synthesis for FPGA
12.8 What Care I Should Take During Synthesis and Prototyping?
12.8.1 Avoid Use of Latches
12.8.2 Avoid Longer Combinational Paths
12.8.3 Avoid the Combinational Loops
12.8.4 Use Wrappers
12.8.5 Memory Modeling
12.8.6 Use of core Generators
12.8.7 Formal Verification
12.8.8 Blocks not Mapping on the FPGA
12.8.9 Better Architecture Design
12.8.10 Use Clock Logic at TOP LEVEL
12.8.11 Bottom-Up Approach
12.9 Important Points to Conclude the Chapter
Reference
13 SOC Debug and Test Scenarios
13.1 SOC Design and Considerations
13.2 Prototyping Challenges and How to Overcome Them?
13.3 Multiple FPGA Architecture and Limiting Factors
13.4 Board Bring-Up and What to Test?
13.5 Debug Plan and Checklist
13.5.1 Basic Tests for the FPGA
13.5.2 Add-On Board Tests
13.5.3 Test the External Logic Analyzer Buses
13.5.4 Multiple FPGA Connectivity and IO Test
13.5.5 Test for the Multiple FPGA Partitioning
13.6 What Are Different Issues on the FPGA Boards
13.7 Testing for the Multiple FPGA Interface
13.8 Debug Logic and Use of Logic Analyzers
13.8.1 Probing Using IO Pins
13.8.2 Use the Test MUX
13.8.3 Use of Logic Analyzer: Practical Scenario (to Detect the Data Packet Is Corrupted)
13.8.4 Oscilloscope to Debug the Design
13.8.5 Debugging Using ILA Cores
13.9 System-Level Verification and Debugging
13.9.1 Hardware/Software Co-verification
13.9.2 Transactors and Transaction-Level Modeling
13.10 SOC Prototyping Future
13.11 Important Points to Conclude the Chapter
Reference
Appendix Xilinx 7 Series Family
Index