𝔖 Bobbio Scriptorium

✦ LIBER ✦

Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay

✍ Scribed by Koren, I.; Koren, Z.; Pradhan, D.K.

Book ID: 111934022
Publisher: IEEE
Year: 1988
Tongue: English
Weight: 811 KB
Volume: 23
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.330

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