Modelling of source-coupled logic gates
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M. Alioto; G. Palumbo; S. Pennisi
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Article
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2002
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John Wiley and Sons
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English
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## Abstract In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a si