It provides an efficient and valuable on hand quick reference to the industry. Depth of the content is also right for marketing and management people who need some knowledge of the field. The book is however, too simple for Electronic Engineer. On the other hand, the pictures inside are not in go
Area Array Interconnection Handbook
β Scribed by Paul A. Totta (auth.), Karl J. Puttlitz, Paul A. Totta (eds.)
- Publisher
- Springer US
- Year
- 2001
- Tongue
- English
- Leaves
- 1250
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Synopsis
Microelectronic packaging has been recognized as an important "enabler" for the solidΒ state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later family or ceramics with matching expansivity to siliΒ con and copper internal wiring was developed as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. Powerful server packages have been deΒ veloped in which the combined chip and package copper wiring exceeds a kilometer. All of this was achieved with the constant objective of minimizing circuit delays through short, efficient interconnects.
β¦ Table of Contents
Front Matter....Pages i-lxviii
History of Flip Chip and Area Array Technology....Pages 1-35
Front Matter....Pages 37-37
Wafer Bumping....Pages 39-116
Wafer-Level Test....Pages 117-148
Known Good Die (KGD)....Pages 149-200
Wafer FinishingβDicing,Picking,Shipping....Pages 201-227
Ceramic Chip Carriers....Pages 228-267
Laminate/HDI Die Carriers....Pages 268-314
Flip-Chip Die Attach Technology....Pages 315-349
Solder Bump Flip-Chip Replacement Technology on Ceramic Carriers....Pages 350-370
Manufacturing Considerations and Tools for Flip Chip Assembly....Pages 371-420
Test and Burn-in Sockets....Pages 421-451
Underfill: The Enabling Technology for Flip-Chip Packaging....Pages 452-499
Reliability of Die-Level Interconnections....Pages 500-548
Front Matter....Pages 549-549
Ceramic and Plastic Pin Grid Array Technology....Pages 551-576
Plastic Ball Grid Array....Pages 577-613
Tape Ball Grid Array....Pages 614-655
Ceramic Ball and Column Grid Arrays....Pages 656-701
Chip Scale Package Technology....Pages 702-761
Assembly of Area Array Components....Pages 762-803
Area Array Component Replacement Technology....Pages 804-837
Front Matter....Pages 549-549
Product Connector Technology....Pages 838-881
Board-Level Area Array Interconnect Reliability....Pages 882-945
Chip Scale Package Assembly Reliability....Pages 946-971
Front Matter....Pages 973-973
Area-array Design Principles....Pages 975-1010
Area Array Leverages: Why and How to Choose a Package....Pages 1011-1030
Interconnections for High-Frequency Applications....Pages 1031-1048
Thermal Performance....Pages 1049-1107
Metallurgical Factors....Pages 1108-1144
Back Matter....Pages 1145-1188
β¦ Subjects
Circuits and Systems; Manufacturing, Machines, Tools; Climate Change; Electrical Engineering
π SIMILAR VOLUMES
*Covers design, packaging, construction, assembly, and application of all three approaches to Area Array Packaging: Ball Grid Array (BGA), Chip Scale Package (CSP), and Flip Chip (FC) *Details the pros and cons of each technology with varying applications *Examines packaging ramifications of high
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