Front Matter......Page 1
27. Process Development, Control, and Organization......Page 0
Foreword......Page 4
Table of Contents......Page 8
Section 1. Packaging Concepts and Design......Page 25
1.1 Introduction and Requirements......Page 26
1.2.2 Perimeter Paralysis......Page 27
1.2.3 Direct Connections......Page 28
1.3.2 Material Compatibility: IC to PWB......Page 30
1.3.6 Facilitate Auto Assembly......Page 31
1.3.9 Thermal Management......Page 32
1.4 Early Package Development......Page 33
1.5.4 Tape Automated Bonding (TAB)......Page 35
1.5.5 Second Level: To PWB......Page 36
1.6.2 Ceramic......Page 37
1.6.3 Plastic......Page 38
1.7.2 Chip Carriers/Platforms......Page 40
1.8.3 Liquid Encapsulants......Page 41
1.9.3 Conductive Adhesives......Page 42
1.11 Future Expectations......Page 43
2.1 The Anatomy of a System......Page 45
2.2 The Electronics Industry in 2020......Page 48
2.2.1 The Structure of the Electronics Industry in 2020......Page 51
3.0 Introduction......Page 55
3.1.1 Importance of Throughput......Page 57
3.1.2 Parallel and Data-Driven Processes......Page 58
3.1.3 Developments in Parallel and Data-Driven Processes......Page 59
3.2.1 Software and Machine Vision Replace Steel......Page 60
3.3 Slow Secondary Processes Become Niche......Page 63
3.4 Throughput, Yield, and Cost Guarantees: Total Solutions......Page 64
3.5.1 Through-Hole Assembly......Page 66
3.5.2 Through-Hole Equipment......Page 67
3.5.3 Nonstandard Automated Assembly......Page 68
3.6 Knowledge......Page 69
3.7 PWB/Flex Line Widths from 6 to 3 Mils as Standard, Microvias, and BUM PWBs Proliferate......Page 70
3.7.1 Multilayer versus Built-Up......Page 72
3.8 Lead-Free Impact......Page 74
3.9 Passives: The Growth Continues......Page 75
3.9.2 What are the Trends in Passives?......Page 76
3.9.3 What is the Future for Passives?......Page 77
3.10 Notes and References......Page 79
4.1.1 Device......Page 80
4.1.2 Wiring or Routing......Page 81
4.2 Overview of Types of Area Array Packages......Page 82
4.3.2 Thermal Management......Page 84
4.3.3 Multiple Chips......Page 85
4.3.6 High Assembly Yield......Page 86
4.4.3 Cost......Page 87
4.4.5 Moisture Absorption......Page 88
4.5.3 Flip Chip (FC)......Page 89
4.6.4 None?......Page 90
4.7.4 Conductive Adhesives......Page 91
4.9.1 Hermetic......Page 92
4.14 Future Expectations......Page 93
5.1 The Fourth Wave of Packaging Innovation......Page 94
5.3 Handset Functional System Integration......Page 97
5.4 CSP to S-CSP Adoption in Handsets......Page 99
5.5 S-CSP Growth: Standards and Infrastructure......Page 100
5.6 Three-Chip Integration in S-CSP Platforms......Page 105
5.7 Flip Chip (FC) and S-CSP Technology Roadmaps......Page 107
5.8 Flip Chip (FC) and Wire-Bond Stack-Die Integration......Page 108
5.9 Conclusion......Page 109
5.10 References......Page 112
6.0 Introduction......Page 113
6.3 Compliant CSP Construction......Page 114
6.3.1 Materials of Construction......Page 115
6.3.4 Other Compliant Β΅BGA Configurations......Page 117
6.3.5 I/O Configurations......Page 118
6.3.7 Adapting to Die Shrink......Page 120
6.4.1 Original Process......Page 121
6.4.2 The Zinger Assembly Process......Page 122
6.4.3 The WAVE Process......Page 123
6.5.1 Software-Modeled RCL Parasitics......Page 124
6.6 Thermal Performance......Page 125
6.7.4 Failure Mechanisms......Page 129
6.8 Summary......Page 133
6.9 References......Page 134
7.0.1 Basics......Page 135
7.0.2 History......Page 136
7.1.1 Problems with Aluminum......Page 138
7.1.2 Types of UBM......Page 139
7.2 Bumping Materials......Page 141
7.2.1 Fusible Bumps......Page 142
7.2.2 Nonfusible Bumps......Page 143
7.3.1 Vacuum Deposition......Page 144
7.3.2 Plating......Page 145
7.3.3 Printing/Stenciling......Page 146
7.3.4 Metal Fluid Jetting......Page 147
7.4.1 Flux......Page 148
7.4.2 Solder Paste......Page 149
7.4.3 Conductive Adhesives......Page 150
7.5.1 Solder Reflow......Page 152
7.5.3 Adhesive Bonding......Page 154
7.6 Encapsulation/Underfill......Page 155
7.6.1 Preapplied Flux/Underfills......Page 156
7.6.2 Postapplied Materials......Page 158
7.7 Substrates for FCs......Page 159
7.7.3 Organic, Flexible, High-Temperature......Page 160
7.8.1 Geometric Considerations......Page 161
7.9 Limitations and Issues......Page 162
7.9.4 Ramifications of Die Shrink......Page 163
7.11.1 Computers and Peripherals......Page 164
7.11.3 Consumer Products......Page 165
7.11.6 Other FC Products......Page 166
7.12 Summary and Conclusions......Page 168
7.13 References......Page 170
8.1 In-Line Cleaning......Page 173
8.3.1 The Centrifugal Cleaning Sequence......Page 174
8.3.2 Solvent Performance......Page 177
8.3.3 Flux/Solvent Performance......Page 178
8.4 Summary......Page 179
9.0 Introduction......Page 180
9.1 Background......Page 181
9.2.1 MEMS Actuation......Page 183
9.4 MEMS Packaging......Page 184
9.4.1 MEMS-Specific Package Designs......Page 186
9.4.2 Packaging Atmosphere Control......Page 188
9.4.3 Getters......Page 189
9.4.4 Surface Control: Friction and Stiction......Page 190
9.4.5 Antifriction Coatings......Page 191
9.5.2 Ink Jet......Page 192
9.5.3 Unique Board Assembly Issues......Page 193
9.6 Optical MEMS: MOEMS......Page 195
9.8 Summary and Conclusions......Page 197
9.9 References......Page 198
10.1 Ceramic Ball Grid Array (CBGA)......Page 199
10.1.1 Chip Carrier......Page 200
10.1.3 Package Interconnection Structure......Page 202
10.2 Ceramic Column Grid Array (CCGA)......Page 203
10.2.2 Die Interconnection and Encapsulation......Page 204
10.2.4 Effect of Pitch Reduction......Page 205
10.3.1 CBGA JEDEC Standards......Page 206
10.3.2 CCGA JEDEC Standards......Page 207
10.5 Comparing CBGA and CCGA......Page 208
10.6.1 Advantages......Page 209
10.6.2 Disadvantages......Page 210
10.7.1 PWB Joining Pads......Page 211
10.7.2 Plated Through-Hole (PTH)......Page 212
10.7.3 Wiring Trace/Solder Mask......Page 213
10.8 Card Assembly Process Requirements......Page 214
10.9.1 Geometric Factors......Page 215
10.9.4 Mechanical Robustness......Page 216
10.10.1 Process Overview......Page 217
10.11.1 CLASP Column Attachment Process for Automation......Page 218
10.11.2 Column Rework......Page 219
10.13 Future Use of CBGA and CCGA Packages......Page 220
10.15 References......Page 221
Section 2. Materials......Page 224
11.1 Description of Electronic Polymers......Page 225
11.2.1 Chains and Links......Page 226
11.2.2 Terms and Properties......Page 227
11.2.4 Thermoplastics versus Thermosets......Page 228
11.3.1 Die-Attach Adhesive......Page 230
11.3.2 Conductive Adhesive for Interconnect......Page 232
11.4.1 Basic Properties of Electronic Encapsulants......Page 233
11.4.2 Epoxy Molding Compounds......Page 239
11.4.4 Thermoplastic versus Thermoset Molding Compounds......Page 241
11.5.1 Preapplied Materials......Page 244
11.5.2 Postapplied Materials......Page 245
11.6.2 CSP Materials......Page 247
11.8 References......Page 248
12.1.1 Methods and Technology......Page 249
12.1.2 Hermetic Package Types......Page 250
12.1.3 Hermetic Seals......Page 255
12.1.4 Package Sealing Technologies......Page 257
12.1.5 Hermeticity Testing......Page 263
12.2.1 Degradation in Devices......Page 266
12.2.4 Mechanisms of Degradation......Page 267
12.3.2 Use of Getters......Page 268
12.5.1 Methods for Hydrogen Capture......Page 269
12.5.4 Application of Getters......Page 270
12.7 References......Page 271
13.1.1 Solder Alloys for Spheres......Page 273
13.2.1 General Characteristics of Solders......Page 275
13.3.1 Stamping and Reflow of Solder Preforms......Page 279
13.3.2 Solder Jetting......Page 280
13.4.1 Quality Criteria......Page 281
13.6.1 Static Electricity Issues......Page 282
13.6.4 Discoloration......Page 283
13.7.1 For Sphere Attachment......Page 284
14.1.1 Physical Properties......Page 285
14.1.2 Metallurgical Properties......Page 286
14.1.3 Mechanical Properties......Page 287
14.2 Solder Paste......Page 288
14.2.1 Solder Powder......Page 289
14.2.3 Chemical and Physical Properties......Page 291
14.2.4 Rheologic Flow Property......Page 292
14.2.5 Solder Paste: Formulation......Page 293
14.2.6 Solder Paste: Performance Parameters......Page 294
14.3 Reflow Soldering......Page 295
14.3.2 Reflow Temperature Profile......Page 296
14.3.3 Effects of Reflow Profile......Page 297
14.3.4 Optimal Reflow Profile......Page 298
14.4 Inert and Reducing Atmosphere Soldering......Page 299
14.4.1 Process Parameters......Page 300
14.5 Printing......Page 302
14.5.2 Stencil Aperture Design versus Land Pattern......Page 303
14.6 Design and Use of Solder Paste for System Reliability......Page 304
14.7.1 Intermetallics versus Solder-Joint Formation......Page 306
14.7.2 Gold-Plated Substrates versus Solder-Joint Formation......Page 308
14.7.4 Solder Balling and Beading......Page 310
14.8 Microstructure......Page 311
14.9 Solder-Joint Integrity......Page 313
14.10 Reliability of BGA Solder Interconnections......Page 315
14.10.5 Other Material: Underfill......Page 316
14.11 Challenges In Modeling Solder-Joint Life Prediction......Page 317
14.13 Lead-Free versus Lead-Bearing Solder......Page 319
14.14.1 Strengthening Approaches......Page 320
14.15 PWB Surface Finishes......Page 321
14.15.2 Basic Processes......Page 322
14.15.3 Metallic Systems......Page 323
14.15.4 Organic Systems......Page 325
14.15.5 Comparison of PWB Surface Finish Systems......Page 326
14.16 Selection Menu: Lead-Free Solder Joint......Page 327
14.17 Lead-Free Recommendations......Page 328
14.18 References......Page 342
15.1.1 Toxicology of Lead and Lead Removal Legislation......Page 345
15.1.3 The Future......Page 346
15.4 How Easy is it to Replace Lead......Page 347
15.4.4 Board Treatments......Page 348
15.5 The Technology Implications of Replacing Lead in Solders......Page 349
15.5.2 Alloy Choice......Page 350
15.5.3 Processing......Page 351
15.6.1 Background......Page 354
15.6.2 Impact of Metal Substitution......Page 355
15.6.5 Yield Loss......Page 356
15.7.1 Asia......Page 357
15.8.1 Rationale......Page 358
15.10 References......Page 359
16.0 Introduction......Page 361
16.1.1 Isotropic Conductive Adhesives......Page 362
16.1.2 Anisotropic Conductive Adhesives......Page 366
16.2 Surface-Mount Assembly......Page 369
16.2.1 ICA Assembly Process......Page 370
16.2.2 ACA Assembly Process......Page 371
16.3 Comparison of Adhesives with Solders......Page 372
16.3.1 Reliability......Page 373
16.4 Flip Chip Assembly......Page 377
16.4.2 FC Attachment......Page 378
16.5 Summary......Page 380
16.6 References......Page 381
Section 3. Equipment and Processes......Page 382
17.1 Concept......Page 383
17.1.2 Next-Generation FC Technology Overview......Page 384
17.1.3 Primary Requirements for IC-to-Package/Substrate Assembly......Page 387
17.2.2 Low-Cost, High-Throughput FC Processing Using No-Flow Underfills......Page 389
17.2.3 Cost Implications of Throughput, Chip Size, and Number of Chips per Panel......Page 392
17.3 High-Throughput FC Processing Using No-Flow Underfllls......Page 394
17.3.1 Process Yield Analysis......Page 397
17.3.2 Yield Analysis Results and Discussion......Page 401
17.3.4 Summary of Process Yield Analysis......Page 405
17.3.5 Reliability Analysis......Page 406
17.3.6 No-Flow Underfill Reliability Results......Page 409
17.3.7 Reliability Data Discussion......Page 416
17.3.9 Failure-Mode Analysis......Page 418
17.3.10 Summary of Failure-Mode Analysis......Page 425
17.4 Wafer-Level FC Processing......Page 426
17.4.1 Desired Coating Characteristics......Page 431
17.4.2 Coating Methods and Materials......Page 433
17.4.3 Chip Imaging and Placement......Page 437
17.4.4 Automated Vision Analysis of Underfill-Coated Chips......Page 439
17.4.5 Analysis of Underfill-Coated Chip Placement Accuracy......Page 443
17.4.6 Wafer-Level FC Processing Summary......Page 445
17.5.1 Potential Void Formation......Page 447
17.5.2 Design Guidelines......Page 449
17.5.3 Placement Force Characterization of Compression Flow Underfill Processing......Page 450
17.5.4 Simulation Analysis of Compression Flow Underfill Processing......Page 452
17.6 Compression Flow Placement Model and Analysis......Page 462
17.7 Modeling and Analysis of Chip Floating......Page 464
17.8 FC Interconnect Yield Analysis During the Reflow Process......Page 470
17.8.1 FC Interconnect Yield Analysis......Page 471
17.8.2 Steady State Forces......Page 472
17.8.3 Solder Force......Page 473
17.8.4 Underfill Force......Page 475
17.8.6 Underfill Viscosity Effect......Page 476
17.8.7 Processing Windows for Complete Chip Collapse......Page 477
17.8.9 Bumps in Contact Due to Placement......Page 478
17.9 Summary......Page 479
17.10 References......Page 481
18.0 Introduction......Page 484
18.1.2 Fluxing Underfills......Page 485
18.2.1 Layout......Page 486
18.2.2 Copper and Solder Mask Requirements......Page 492