Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift
โฆ LIBER โฆ
[ACM Press the 2007 international symposium - Portland, OR, USA (2007.08.27-2007.08.29)] Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 - Variable-latency adder (VL-adder)
โ Scribed by Chen, Yiran; Li, Hai; Li, Jing; Koh, Cheng-Kok
- Book ID
- 125810047
- Publisher
- ACM Press
- Year
- 2007
- Weight
- 318 KB
- Category
- Article
- ISBN
- 1595937099
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