[ACM Press the 2007 international symposium - Portland, OR, USA (2007.08.27-2007.08.29)] Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 - Low power FPGA design using hybrid CMOS-NEMS approach
โ Scribed by Zhou, Yu; Thekkel, Shijo; Bhunia, Swarup
- Book ID
- 118010512
- Publisher
- ACM Press
- Year
- 2007
- Weight
- 554 KB
- Volume
- 0
- Category
- Article
- ISBN
- 1595937099
No coin nor oath required. For personal study only.
โฆ Synopsis
Higher integration density of nanoscale CMOS causes two major design challenges in SRAM-based Field Programmable Gate Array (FPGA) designs: large power dissipation (contributed by both leakage and dynamic power) and reduced reliability of operation. In this paper, we propose a hybrid design approach for SRAM-based FPGA that can leverage on non-volatile carbon nanotube based nano electro-mechanical systems (NEMS) switches for low static and dynamic power. Simulations show that the proposed CMOS-NEMS lookup table (LUT) based circuits can achieve a reduction of up to 91% in total power at iso-performance, compared to the conventional CMOS-based LUT circuits.
๐ SIMILAR VOLUMES
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) technique for NBTI tolerance. By detecting the circuit failure on-the-fly, the proposed VL-adder can automatically shift