Machine learning and data mining are gaining increasing attentions of the computing society. FPGA provides a highly parallel, low power, and flexible hardware platform for this domain, while the difficulty of programming FPGA greatly limits its prevalence. MapReduce is a parallel programming framewo
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[ACM Press the 18th annual ACM/SIGDA international symposium - Monterey, California, USA (2010.02.21-2010.02.23)] Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10 - FPMR
โ Scribed by Shan, Yi; Wang, Bo; Yan, Jing; Wang, Yu; Xu, Ningyi; Yang, Huazhong
- Book ID
- 126454343
- Publisher
- ACM Press
- Year
- 2010
- Tongue
- English
- Weight
- 903 KB
- Category
- Article
- ISBN
- 160558911X
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This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to t