This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to t
โฆ LIBER โฆ
[ACM Press the 2007 ACM/SIGDA 15th international symposium - Monterey, California, USA (2007.02.18-2007.02.20)] Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays - FPGA '07 - GlitchLess
โ Scribed by Lamoureux, Julien; Lemieux, Guy G.; Wilton, Steven J. E.
- Book ID
- 118045607
- Publisher
- ACM Press
- Year
- 2007
- Tongue
- English
- Weight
- 433 KB
- Volume
- 0
- Category
- Article
- ISBN
- 1595936009
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