A survey of device reliability concerns for LV/LP IC technologies
โ Scribed by K.F. Galloway; R.D. Schrimpf
- Book ID
- 104306467
- Publisher
- Elsevier Science
- Year
- 1997
- Tongue
- English
- Weight
- 789 KB
- Volume
- 39
- Category
- Article
- ISSN
- 0167-9317
No coin nor oath required. For personal study only.
โฆ Synopsis
This survey paper will discuss reliability considerations for low voltage/low power (LV/LP) integrated circuit technologies with a focus on device level issues. The growing LV/LP market will continue to be dominated by scaled CMOS. However, CMOS on SOI (silicon on insulator) may grow in importance due to improved performance when compared to bulk, low power CMOS. Aggressive low voltage/ low power technologies may alter the relative importance of current reliability concerns. This survey will attempt to assess the effect of a LV/LP roadmap on device reliability.
๐ SIMILAR VOLUMES
We have developed low standby power (LSTP) FET utilizing HfSiON dielectric. Due to optimizations of channel and offset spacer structure, we could put threshold voltage of pFET into the place of LSTP region, working through the Fermilevel-pinning effect. This resulted in the reduction of propagation