✦ LIBER ✦

A statistical theory of digital circuit testability

✍ Scribed by Seth, S.C.; Agrawal, V.D.; Farhat, H.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design of modular digital circuits for t

✍ Kusiak, A.; Huang, C.-C. 📂 Article 📅 1997 🏛 IEEE ⚖ 224 KB

Physical design of testable CMOS digital

✍ de Sousa, J.J.H.T.; Goncalves, F.M.; Teixeira, J.P. 📂 Article 📅 1991 🏛 IEEE 🌐 English ⚖ 1002 KB

Design for testability of digital combin

✍ Fadi N. Sibai 📂 Article 📅 1991 🏛 Elsevier Science 🌐 English ⚖ 466 KB

Addendum to “Synthesis of robust delay-f

✍ Devadas, S.; Keutzer, K. 📂 Article 📅 1996 🏛 IEEE 🌐 English ⚖ 241 KB

Statistical Timing for Parametric Yield

✍ Jess, J.A.G.; Kalafala, K.; Naidu, S.R.; Otten, R.H.J.M.; Visweswariah, C. 📂 Article 📅 2006 🏛 IEEE 🌐 English ⚖ 535 KB

Examination of the statistical method in

✍ Ivan Gutman 📂 Article 📅 1989 🏛 Springer Vienna 🌐 English ⚖ 257 KB