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Addendum to “Synthesis of robust delay-fault testable circuits: Theory”

✍ Scribed by Devadas, S.; Keutzer, K.

Book ID: 119778045
Publisher: IEEE
Year: 1996
Tongue: English
Weight: 241 KB
Volume: 15
Category: Article
ISSN: 0278-0070
DOI: 10.1109/43.494708

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