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A Novel Multiplexer-Based Low-Power Full Adder

โœ Scribed by Jiang, Y. ;Al-Sheraidah, A. ;Wang, Y. ;Sha, E. ;Chung, J.-G.

Book ID
118189869
Publisher
IEEE
Year
2004
Tongue
English
Weight
353 KB
Volume
51
Category
Article
ISSN
1057-7130

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Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8 ร‚ 8 implementation